This invention relates to charge coupled device memories (CCD memories), and more particularly to a unique CCD memory architecture which results in greater storage capacity.
CCD memories are used in digital computer systems for storing information in binary form. These computer systems have an almost infinite variety of applications, and thus the demand for such memories is large.
Presently available CCD memories have access times of approximately 100 microseconds. This is slower than the access time of MOS/T.sup.2 L memories, but faster than the access time of disc/tape memories. For example, the access time is approximately 50 to 300 nanoseconds for the former, and approximately 10 milliseconds to several seconds for the latter. CCD memories are therefore used as fast auxiliary memories to tapes and discs. They are also used as "fast memories" in computers where the higher MOS/T.sup.2 L speeds are not required.
A critical parameter for the CCD memory chip is the number of bits per chip. This is because the tendency of computer systems over the years has been to require larger amounts of memory storage. Thus, various design efforts have been employed to increase the number of bits per chip. As a result, sixteen thousand bits per chip is not uncommon today. See, for example, IEEE Journal of Solid-State Circuits, Feb. 76, pp 1-74. And efforts continue to be made to increase this figure.
A popular architecture for the CCD memory is the serial-parallel-serial (SPS) organization. Binary bits are first serially loaded into a shift register. When the register is full, the bits are loaded in parallel into a first in-first out stack. The bits are then moved in parallel through column transfer channels within the stack. At the stack output, they are loaded in parallel into another shift register. The bits are then shifted serially into a detection device.
A major advantage of the SPS architecture is that it requires only one detection device, which thus can be relatively sophisticated yet occupy a relatively small amount of total chip area. On this point see, for example, Charge Transfer Devices Carlo H. Sequin and Michael F. Tompsett, p. 245, 1975. However, a major disadvantage is that chip space between the column transfer channels of the stack is wasted. This is because the column transfer channels must line up with the parallel output/inputs of the two registers; and the spacing between successive outputs/inputs of the register is larger than that which is required to physically build the column transfer channels.
In the past, one technique which has been employed to reduce the space between successive outputs/inputs of the registers is to provide two outputs/inputs per stage, instead of the usual one. But the problem with this technique is that it requires a complicated clocking scheme to control its operation. The input register must be loaded twice to fill the column transfer channels, and the output register must be unloaded twice to empty the column transfer channel.
Another technique which has been employed to increase the number of memory storage bits per chip is to utilize a serpentine architecture. This architecture utilizes plurality of shift registers, interconnected in series, and thus eliminates this column channel spacing problem. However, it creates a new problem. The serial path for each bit is lengthened, and thus refresh stages must be added at intermediate points to regenerate the signal as it passes through the serial chain.
In view of the deficiencies of the prior art, it is therefore one objective of this invention to provide an improved SPS CCD memory.
Another objective is to provide a SPS CCD memory with increased storage capacity.
Still another objective is to provide an SPS CCD memory having reduced space between the column transfer channels.